1. Field of the Invention
The present invention relates to a semiconductor memory which requires refresh operations to retain data written in its memory cells.
2. Description of the Related Art
Such semiconductor memories as a DRAM having dynamic memory cells need to perform refresh operations with a predetermined cycle in order to retain data in their memory cells. The frequency of refresh operations may be reduced by increasing signal quantities (charges) written in the memory cells. Hence, the greater the signals quantities to be written to the memory cells are, the longer the data retention time is and the lower the power consumption is. On the other hand, at the time of rewriting data during read operations and in write operations, writing greater quantities of signals to the memory cells lead to extending the operating time (cycle time).
As mentioned above, securing the data retention time and reducing the cycle time are goals which coincide with each other. Thus, it has been difficult for semiconductor memories such as a DRAM to achieve both securing data retention time and reducing cycle time at the same time.
Conventionally, in semiconductor memories that are oriented to low power consumption, signal quantities to be written to the memory cells are increased to lower the refresh frequency in exchange for extended cycle time. In semiconductor memories oriented to high-speed access, signal quantities to be written to the memory cells are not increased, and the cycle time is reduced in return for higher refresh frequency.
It is an object of the present invention to reduce the cycle time of a semiconductor memory having dynamic memory cells without increasing the power consumption.
According to one of the aspects of the semiconductor memory of the present invention, an operation control circuit activates sense amplifiers in response to a read request, a write request, and a refresh request to memory cells. The sense amplifiers amplify quantity of signals in data to be written to the memory cells. The memory cells require refresh to retain data. The operation control circuit also sets timing of the sense amplifiers inactivates to correspond to a timing a maximum possible quantity of signals, which is amplified by the sense amplifiers operating in response to the refresh request, is transmitted to the memory cells. Consequently, in a refresh operation corresponding to the refresh request, data read from the memory cells is fully written to the memory cells again. In a read operation corresponding to the read request and a write operation corresponding to the write request, data is not fully written to the memory cells. Tailoring the activating period of the sense amplifiers to the refresh operating time, however, allows reduction in the read operating time and the write operating time.
A refresh control circuit cyclically outputs a refresh request signal as the refresh request for refreshing the memory cells. The refresh control circuit extends the cycle of generating the refresh request signal after a predetermined number of refresh requests are generated consecutively without intervention of the read request or the write request so that the memory cells are all refreshed. When the refresh requests occur consecutively (standby mode), the refresh frequency can thus be lowered to reduce power consumption. As a result, the cycle time can be reduced without increasing the power consumption in the standby mode.
According to another aspect of the semiconductor memory of the present invention, the refresh control circuit includes a consecutive refresh judgement circuit and a refresh timer. The consecutive refresh judgement circuit activates a cycle changing signal when a refresh address counter, for generating a refresh address designating a memory cell to refresh, goes through a single round without the intervention of the read request or the write request to the memory cells. The refresh timer extends a length of the cycle for generating the refresh request signal while the cycle changing signal is activated, so that the cycle is longer than the length of a cycle while the cycle changing signal is inactivated. The time of the cycle can thus be reduced by a simple logic circuit, without increasing the power consumption during the standby mode.
According to another aspect of the semiconductor memory of the present invention, the cycle changing signal output from the consecutive refresh judgement circuit is output to the exterior through an external terminal. In accordance with the cycle changing signal, the cycle for supplying an external refresh request can be extended so that a semiconductor memory capable of being supplied with the refresh request even from the exterior is reduced in cycle time without increasing power consumption during the standby mode.
According to another aspect of the semiconductor memory of the present invention, the refresh control circuit includes a refresh counter and a refresh timer. The refresh counter is reset in accordance with the read request signal or the write request to the memory cells, and counts in accordance with the refresh request signal. The refresh counter activates a cycle changing signal when its counter value reaches a predetermined number. The refresh timer extends the length of the cycle for generating the refresh request signal while the cycle changing signal is activated, so that the cycle is longer than the length of a cycle while the cycle changing signal is inactivated. The cycle time can thus be reduced by a simple logic circuit without any increase in power consumption in the standby mode.
According to another aspect of the semiconductor memory of the present invention, a plurality of word lines are connected to the memory cells, respectively. One of the word lines is selected in accordance with an address signal. The operation control circuit sets selecting periods for the word lines to be equal, in a read operation corresponding to the read request, a write operation corresponding to the write request, and a refresh operation corresponding to the refresh request. Since the selecting period of the word lines need not be changed depending on the type of operation, the operation control circuit can be configured simply.
According to another aspect of the semiconductor memory of the present invention, the refresh request is recognized only by the refresh request signal output from the refresh control circuit. A refresh operation is performed on the memory cells only in response to the refresh request signal, without receiving a command signal from an external terminal. That is, a semiconductor memory capable of performing a refresh operation automatically in the inside can be reduced its cycle time without any increase in power consumption in the standby mode.
According to another aspect of the semiconductor memory of the present invention, a plurality of word lines are connected to the memory cells, respectively. One of the word lines is selected in accordance with an address signal. The operation control circuit sets a selecting period of the word lines in at least one of a read operation corresponding to the read request or a write operation corresponding to the write request, to be shorter than the selecting period for the word lines in a refresh operation corresponding to the refresh request. Consequently, the cycle time can be further reduced without any increase in power consumption in the standby mode.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit sets a timing for the word lines to be deselected during at least either of the read operation and the write operation at earlier than the deselecting timing of the word lines in the refresh operation. Consequently, in the cycle time can be further educed without any increase the power consumption in standby mode.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit sets an activating period of the sense amplifiers in at least either of a read operation corresponding to the read request and a write operation corresponding to the write request at shorter than the activating period of the sense amplifiers in a refresh operation on the memory cells. Consequently, the cycle time can be further reduced with no increase in the power consumption in standby mode.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit recognizes the refresh request when the refresh request signal is output from the refresh control circuit or a refresh command is supplied through an external terminal. That is, in a semiconductor memory which automatically performs refresh operations inside as well as in response to refresh requests from the exterior, the cycle time can be reduced without any increase of power consumption in the standby mode.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit outputs a sense amplifier activating signal for activating the sense amplifiers in response to the read request, the write request, and the refresh request. The sense amplifiers are connected to a power supply line in response to the sense amplifier activating signal. The maximum possible quantity of signals to be amplified by the sense amplifiers is a quantity corresponding to a power supply voltage of the power supply line. Through the sense amplifiers, signal quantities to be written to the memory cells are brought into correspondence with the power supply voltage. After the start of operation of the sense amplifiers, data can thus be written to the memory cells at high speed. As a result, the refresh operation, the read operation, and the write operation can be performed at high speed.